A static random access memory (SRAM) cell includes a pair of cross-coupled inverters for storing a bit as one of two stable logic states. Each cross-coupled inverter comprises a serial stack of a PMOS transistor and a NMOS transistor. This configuration greatly reduces static power consumption since one of the transistors in each cross-coupled inverter is always off in both logic states. Moreover, SRAM processing speed is relatively high since the cross-coupled inverters actively drive their logic states onto corresponding bit lines. In contrast, the passive capacitor in a dynamic random access memory (DRAM) cell has no such drive. DRAM processing speed is thus relatively slow compared to SRAM.
A typical single port SRAM cell (also denoted as a “bitcell”) is made up of six transistors: four transistors for the pair of cross-coupled inverters, and two additional access transistors that control the access to the bitcell during read and write operations. The two access transistors are enabled by an assertion of a word line and control the connection of the bitcell to a pair of complementary bit lines used to transfer data for both read and write operations.
SRAMs with multiport memory cells further enhance operation flexibility. In a conventional multiport SRAM, additional access transistors are used to form the extra access ports. For example, FIG. 1 illustrates a conventional multiport bitcell 100 that includes cross-coupled inverters 101 and 102. Inverter 102 drives a node Q for bitcell 100 whereas inverter 101 drives a complement node QB. In this embodiment, there are two write word lines WWL0 and WWL1 corresponding to two separate write ports. Word line WWL0 drives the gates of access transistors 110 and 112 to couple node Q to a complement write bit line WBLB0 and to couple node QB to a write bit line WBL0. Similarly, word line WWL1 drives the gates of access transistors 120 and 122 to couple node Q to a complement write bit line WBLB1 and to couple node QB to a write bit line WBL1.
Read operations occur through four read ports that include read word lines RWL0, RWL1, RWL2, and RWL3 and corresponding read bit lines RBL0, RBL1, RBL2, and RBL3. Each read bit line couples to a corresponding pair of serially arranged read access transistors. One read access transistor in each pair has its gate driven by the corresponding read word line. Depending upon the read port, another read access transistor has its gate driven by Q node or the QB node. For example, read word line RWL0 drives the gate of a read access transistor 130 that is serially coupled between bit line RBL0 and a read access transistor 135 having its gate driven by the Q node. The source of read access transistor 135 couples to ground. Should read word line RWL0 be asserted, the voltage on read bit line RBL0 after its precharging will depend upon the logic state of node Q. If the Q node was charged to a power supply voltage VDD, then read access transistors 130 and 135 will both be on such that read bit line RBL0 discharges towards ground. Conversely, if the Q node was discharged, then read access transistor 135 is switched off such that read bit line RBL0 can maintain its charge. In this fashion, a sense amplifier (not illustrated) coupled to read bit line RBL0 can determine the logical state of the Q node based upon whether read bit line RBL0 is discharged towards ground or floats. The reading of the logical state of the Q node (or the QB node) occurs analogously with regard to the remaining read bit lines RBL1, RBL2, and RBL3.
In a write operation for one of the write ports, the corresponding write bit line is either charged to the power supply voltage VDD or grounded depending upon the logical value to be written into bitcell 100 whereas the corresponding complement write bit line is charged or discharged in a complementary fashion. For example, a binary one may correspond to charging a write bit line to VDD and discharging the corresponding complement write bit line to ground (VSS). In such an embodiment, a binary zero would then correspond to charging the complement bit line to VDD and grounding the bit line. But note the issue that occurs if a write operation needs to change the stored value in bitcell 100. For example, suppose the stored logic state for bitcell 100 is such that the QB node is charged to VDD whereas the Q node is discharged to VSS. In such a state, the PMOS transistor (not illustrated) in inverter 101 is fully on—it is this transistor that is charging the QB node to VDD. Suppose a write operation is then initiated by asserting write word line WWL0. Access transistor 110 will then couple the QB node to write bit line WBL0 while access transistor 112 couples the Q node to a complement write bit line WBLB0. If the data value to be written is such that write bit line WBL0 is grounded whereas complement write bit line WBLB0 is charged to VDD, the logic states for the nodes QB and Q must be “flipped” such that node QB becomes grounded and node Q is charged to VDD. But that means NMOS access transistor 110 must fight with the PMOS transistor in inverter 101 at the onset of the write operation since NMOS access transistor 110 is trying to pull the QB node low by discharging it to the grounded bit line WBL0 whereas the inverter's PMOS transistor is trying to pull the QB node high.
To complete the write operation by flipping the stored logic state, an NMOS access transistor such as transistor 110 must be relatively strong in relation to the inverter's PMOS transistor. But as semiconductor process technology pushes into the deep submicron regime, a PMOS transistor tends to be stronger than a corresponding NMOS transistor of the same size. It is thus more and more difficult for an access transistor to flip the stored logic state of a bitcell as transistor dimensions are reduced. The power supply voltage VDD must be held relatively high and the write operation duration must have a sufficient length so that the NMOS transistor has the drive to overcome the inverter's PMOS transistor. To increase write operation speed, various write assist schemes have been developed that add complexity and decrease circuit density. Moreover, the required level for the operating voltage increases power consumption
Accordingly, there is a need in the art for multiport SRAM cells having improved write speed with reduced power consumption and improved layout.